Energy efficiency remains one of the foremost challenges in modern computing, spanning from edge IoT devices to high-performance data centers.
Conventional CMOS-based architectures are approaching fundamental physical limits, while the "memory wall" — data transfers between processor and memory accounting for 70 to 90% of total system energy — continues to worsen with the ever-growing demands of data-intensive workloads such as deep neural networks and signal processing pipelines.
In-Memory Computing (IMC) has emerged as a disruptive paradigm to overcome these bottlenecks by embedding arithmetic operations directly within memory arrays, drastically reducing data movement.
In this landscape, ferroelectric field-effect transistors (FeFETs) stand out as particularly compelling devices: fully compatible with standard CMOS fabrication processes, non-volatile, reconfigurable, and capable of storing intermediate polarization states — a property that naturally enables ternary logic within a single device.
The Post-Doctoral position will cover at least one of the following tasks:Design Standard Cell Technology Library based on FeFET devices developed at INL in order to be used with synthesis flow.
Design and optimize ternary arithmetic units (multiply-accumulate units, adders, comparators) based on the FeFET ternary gate library developed within the project, targeting area, power, and timing closure under realistic process constraints.
Investigate hardware/software co-design strategies for mapping real-world applications — particularly convolutional neural networks (CNNs) and signal processing kernels — onto the ternary IMC fabric, exploiting approximate computing techniques to trade precision for energy efficiency.
Assess and benchmark the energy, perform.