Analog Layout Engineer (Lead)

At Kandou, we are redefining the economics of AI infrastructure.

Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient.

Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

 Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

 Job title: Analog Layout Engineer (Lead)Location: EU/CH/UK ResponsibilityPosition in custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed chip to chip communication links (SerDes up to and beyond 28Gb/s and/or memory IO) in advanced semiconductor technology nodesLayout and verification of very high-speed analog circuitsInteract closely with the design team to understand.

Requisitos

and implement solutionsSupport IP and chip level integrationSupport and interact with customers on requirements, and IP deliveryExposure to flip-chip package technologiesExperienceMust have experience in custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or HF/RF circuitsMust have expertise in layout of high-speed/frequency circuits like amplifiers, oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks like biasing, buffers, regulators, filters, data converters, etc.Understanding of layout approaches and techniques for high-speed circuits, matching constraints, minimization of parasitics, power grids and ESD requirementsExperience on modern semiconductor process technologies including 28nm, 14/16nm, 7nmUser of EDA tool for design and verification like Cadence ...