Senior Hardware Design Engineer

Meet Arago and the AragoniansArago is an AI and computer hardware company whose mission is to drive the course of history forward.

We do so by accelerating breakthroughs at the intersection of AI and semiconductors.

Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs.

Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements.

Our work is guided by these core principles:Do great things: we deliver work we’re proud to sign our name to.

High velocity: speed matters.

We move quickly, one step at a time.

One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie.

Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders.

 What you’ll doDesign and verify custom digital hardware components and architectures that enable high-performance, tightly integrated computation workloads and interface Arago’s custom tensor unit for advanced AI/ML applications.

 ResponsibilitiesDesign, implement, and verify RTL blocks for memory, control, and compute subsystems within Arago’s custom multiphysics computation unit.

• Collaborate with Arago’s system software and architecture teams to define block-level specifications and ensure alignment with performance and integration goals.
• Develop and maintain functional verification infrastructure to validate design correctness across simulation and hardware testbenches.
• Support synthesis, timing analysis, and backend integration, working closely with Arago’s physical design and CAD engineers.

Contribute to architectural exploration and hardware-software co-design efforts to shape future iterations of Arago’s compute platform.