Emerging computing technologies – non-volatile and ferroelectric memories, analog and digital in-memory computing, silicon photonics, 3D integration, and heterogeneous chiplets – offer major gains in energy efficiency, latency, bandwidth, and functionality.
Their potential cannot, however, be established from device or circuit results alone: it requires a rigorous link between technology characteristics, architectural choices, workload mapping, and application-level figures of merit.
The Electronics group at the Lyon Institute of Nanotechnology (INL) is seeking a (m/f) postdoctoral researcher to develop an open, modular and extensible system-level evaluation framework for design space exploration (DSE) and system-design-technology co-optimization (SDTCO) of emerging computing architectures.
The focus is at the interface of computer architecture, accelerator design, performance modelling and hardware-software codesign, while making systematic use of lower-level device, circuit and array results so that architectural conclusions remain physically credible.
The objective is to convert low-level results – compact models, measured or simulated KPIs, variability and reliability constraints, and multi-objective Pareto fronts – into parameterized architectural models supporting efficient exploration of accelerators for emerging AI workloads.
The framework must enable both bottom-up projection, from device/circuit/array choices toward system performance, and top-down constraint propagation, from targets for energy, latency, throughput, accuracy, robustness and area toward technology and circuit.
It will consolidate ongoing INL activities in predictive system assessment, DTCO, emerging memories, compute-in-memory and photonic computing, integrating or extending existing components with emphasis on openness, reproducibility and reusability.
A core scientific challenge is to represent cross-layer trade-offs without hiding their origin: rather than isolated energ.